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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Designer'sTM Data Sheet
TMOS E-FET.TM High Energy Power FET D2PAK for Surface Mount
N-Channel Enhancement-Mode Silicon Gate
This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage-blocking capability without degrading performance over time. In addition, this advanced TMOS E-FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Robust High Voltage Termination * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage -- Continuous -- Non-Repetitive (tp 10 ms) Drain Current -- Continuous -- Continuous @ 100C -- Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C (1) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy -- Starting TJ = 25C (VDD = 50 Vdc, VGS = 10 Vdc, Peak IL = 2.0 Apk, L = 95 mH, RG = 25 ) Thermal Resistance -- Junction to Case -- Junction to Ambient -- Junction to Ambient (1)
MTB2N60E
Motorola Preferred Device
TMOS POWER FET 2.0 AMPERES 600 VOLTS RDS(on) = 3.8 OHM
(R)
D
G CASE 418B-02, Style 2 D2PAK S
Symbol VDSS VDGR VGS VGSM ID ID IDM PD
Value 600 600 20 40 2.0 1.3 7.0 50 0.4 2.5 - 55 to 150 190 2.5 62.5 50 260
Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts C mJ C/W
TJ, Tstg EAS RJC RJA RJA TL
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds (1) When surface mounted to an FR4 board using the minimum recommended pad size.
C
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.
E-FET and Designer's are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
(c)Motorola TMOS Power MOSFET Transistor Device Data Motorola, Inc. 1996
1
MTB2N60E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 600 Vdc, VGS = 0 Vdc) (VDS = 480 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 1.0 Adc) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 2.0 Adc) (VGS = 10 Vdc, ID = 1.0 Adc, TJ = 125C) Forward Transconductance (VDS = 50 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 400 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (VDD = 300 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 18 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage Reverse Recovery Time INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. LD -- LS -- 7.5 -- 3.5 -- nH nH (IS = 2.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) VSD trr -- 340 -- -- -- 1.0 0.9 1.6 -- Vdc ns -- -- -- -- -- -- -- -- 12 21 30 24 13 2.0 6.0 5.0 -- -- -- -- -- -- -- -- nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss -- -- -- 435 100 20 -- -- -- pF VGS(th) 2.0 -- RDS(on) VDS(on) -- -- gFS 1.0 -- -- -- 8.2 8.4 -- mhos -- 3.1 8.5 3.0 4.0 -- 3.8 Vdc mV/C Ohm Vdc V(BR)DSS 600 -- IDSS -- -- IGSS -- -- -- -- 0.25 1.0 100 nAdc -- 480 -- -- Vdc mV/C Adc Symbol Min Typ Max Unit
2
Motorola TMOS Power MOSFET Transistor Device Data
MTB2N60E
TYPICAL ELECTRICAL CHARACTERISTICS
4 ID , DRAIN CURRENT (AMPS) TJ = 25C VGS = 10 V 8 7V ID , DRAIN CURRENT (AMPS) 6 VDS 10 V
3 6V 2 5.5 V 1 5V 0 0 4 8 12 16 20
4 TJ = 100C -55C 25C 0 0 2 4 6 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10
2
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
12 VGS = 10 V 100C
4.5 4.3 4.1 3.9 3.7 3.5 3.3 3.1 2.9 2.7 2.5 0 0.5 1 1.5 2 2.5 3 ID, DRAIN CURRENT (AMPS) 3.5 4 15 V VGS = 10 V TJ = 25C
8 TJ = 25C
4 -55C
0
0
1.5
3 ID, DRAIN CURRENT (AMPS)
4.5
6
Figure 3. On-Resistance versus Drain Current and Temperature
1000 VGS = 10 V ID = 1 A 2 I DSS , LEAKAGE (nA) 100
Figure 4. On-Resistance versus Drain Current and Gate Voltage
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
2.5
VGS = 0 V TJ = 125C 100C
1.5
1
10
0.5
0 - 50
- 25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
150
1 0 100 300 500 200 400 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 600
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
MTB2N60E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
800 700 600 C, CAPACITANCE (pF) 500 400 300 200 100 0 10
VDS = 0 V Ciss
VGS = 0 V
TJ = 25C
1000 Ciss C, CAPACITANCE (pF) 100 Coss 10 Crss 1 TJ = 25C VGS = 0 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000
Ciss Crss
Coss Crss 5 0 5 10 15 20 25
0.1
VGS VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
Figure 7b. High Voltage Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
MTB2N60E
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) 15 12 VDS 500 TJ = 25C ID = 2 A 400 QT Q1 Q2 3 VGS Q3 4 8 12 16 20 100 0 VDS = 100 V VDS = 250 V VDS = 400 V 1000 TJ = 25C ID = 2 A VDS = 300 V VGS = 10 V td(off) tf tr
100 t, TIME (ns)
9 6
300 200
td(on) 10
00
1 1 10 100 RG, GATE RESISTANCE (OHMS) 1000
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
2.0 1.8 I S , SOURCE CURRENT (AMPS) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 VGS = 0 V TJ = 25C
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain- to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
5
MTB2N60E
SAFE OPERATING AREA
EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 10 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 1 100 s 1 ms 10 ms 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 1000 dc 10 s 200 Peak IL = 2 A VDD = 50 V
150
100
50
0.01 0.1
0 25
50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)
150
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
1 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 0.00001 0.0001 0.001 0.01 t, TIME (SECONDS) t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1 10
t2 DUTY CYCLE, D = t1/t2 0.1
Figure 13. Thermal Response
3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (C) 150
RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
Figure 15. D2PAK Power Derating Curve
6
Motorola TMOS Power MOSFET Transistor Device Data
MTB2N60E
INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface
0.33 8.38
between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.42 10.66
0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02
0.24 6.096
inches mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = TJ(max) - TA RJA dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16.
70 R JA , Thermal Resistance, Junction to Ambient ( C/W) Board Material = 0.0625 G-10/FR-4, 2 oz Copper 60 2.5 Watts TA = 25C
50 3.5 Watts 40 30 20 5 Watts
The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. PD = 150C - 25C = 2.5 Watts 50C/W The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal CladTM. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.
0
2
4
6 8 10 A, Area (square inches)
12
14
16
Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical)
Motorola TMOS Power MOSFET Transistor Device Data
7
MTB2N60E
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.
Figure 17. Typical Stencil for DPAK and D2PAK Packages
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds.
* When shifting from preheating to soldering, the maximum * After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. temperature gradient shall be 5C or less.
8
Motorola TMOS Power MOSFET Transistor Device Data
CC CC CC CC
CCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
SOLDER PASTE OPENINGS
STENCIL
MTB2N60E
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177 -189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.
STEP 1 PREHEAT ZONE 1 "RAMP" 200C
STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP"
DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C
STEP 5 STEP 4 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 "SPIKE" "SOAK" 170C 160C
STEP 6 VENT
STEP 7 COOLING 205 TO 219C PEAK AT SOLDER JOINT
150C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)
100C 100C
140C
DESIRED CURVE FOR LOW MASS ASSEMBLIES 50C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 18. Typical Solder Heating Profile
Motorola TMOS Power MOSFET Transistor Device Data
9
MTB2N60E
PACKAGE DIMENSIONS
C E B
4
V
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.575 0.625 0.045 0.055 MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 14.60 15.88 1.14 1.40
A
1 2 3
S
STYLE 2: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN
-T-
SEATING PLANE
K G D H
3 PL M
J
DIM A B C D E G H J K S V
0.13 (0.005)
T
CASE 418B-02 ISSUE B
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10
Motorola TMOS Power MOSFET Transistor Device Data MTB2N60E/D
*MTB2N60E/D

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